Analog CMOSLecture 12, Slides of Analog Electronics

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ECE 315/

Analog CMOS Circuit Design

Lecture 12

2 Outline

• Mid-term examination
  • 2:30-4:30 p.m., September 20, 2017
  • Allowed items: Course textbooks; Calculator
• Basic Differential Pair
  • Impact of Finite Output Impedance of Current Source
  • Impact of Asymmetries in the Circuit
  • Common-mode rejection ratio
• Differential Pair with MOS Loads
• Glibert Cell

• M

1 and M 2 are “in parallel”

• Can be reduced to one composite device with twice the width, bias current and transconductance
• “Common - mode gain” of the circuit is ( λ = γ = 0)
• Input CM variations disturb bias points (introduces common- mode gain), and affect small-signal gain and output swings Impact of Finite O/P Impedance Current Source

Impact of R D Mismatch & Finite O/P Impedance

• Since the circuit is not fully symmetric, change in Vin,CM results in variation in differential output
• RD1 = RD , RD2 = RD + ΔRD, where ΔRD denotes a small mismatch and circuit is otherwise symmetric
• M 1 and M 2 operate as one source follower, changing V P by (a ssume λ = γ = 0)

• Common-mode response depends on output impedance of tail current source and asymmetries in the circuit
• Two effects:
  • Variation of output CM level (in the absence of mismatches)
  • Conversion of input CM variations to output differential components (more severe)
• Analyze common-mode response considering mismatches Impact of R D Mismatch & Finite O/P Impedance

Common-mode to differential conversion

• CM to differential conversions become significant at high frequencies
• Total capacitance shunting the tail current source introduces larger tail current variations
• This capacitance arises from parasitics of the current source and source-bulk junctions of M 1 and M 2

• Thus,
• We now obtain the output voltages as
• The differential component at the output is Impact of Transistor Mismatch

• The circuit converts input CM variations to a differential error by a factor of
• ACM-DM denotes common-mode to differential-mode conversion and Δg m = g m - g m Impact of Transistor Mismatch

Differential Pair with MOS Loads

• Differential pairs can employ diode-connected or current- source loads
• For diode-connected loads, small-signal differential gain is (half-circuit analysis):  N and P subscripts denote NMOS and PMOS respectively

Differential Pair with MOS Loads

• Expressing g mN and g mP in terms of device dimensions,
• For current-source loads, the gain is

Differential Pair with MOS Loads

• gm of load devices M 3 and M 4 can be lowered by reducing their current instead of ( W/L ) P for the same overdrive voltage
• For I D

= I

D

= 0.8 I

D

= 0.8 I

D  ID3 and ID4 are reduced by a factor of 5  For a given overdrive, g mP is lowered by the same factor  Differential gain is five times that of the case without auxiliary PMOS current sources (assume λ = 0)

Cascode Differential Pair

• Small-signal voltage gain of differential pair with current-source loads can be increased via cascoding
• Increases output impedance of both NMOS and PMOS devices
• But at the cost of lower voltage headroom
• The gain is calculated using the half-circuit technique

Gilbert Cell

• Differential pair whose gain is controlled by a control voltage
• Behaves as a Variable Gain Amplifier (VGA)
• Used where signal amplitude experiences large variations and hence inverse changes in gain are required
• Control voltage V cont controls the tail current and hence gain
• A v

= V

out

/ V

in is variable

• Zero for ID3 = 0
• Maximum defined by voltage headroom limitations and device dimensions

Gilbert Cell

• An amplifier whose gain can be continuously varied from a negative to a positive value
• Figure shows two differential pairs that amplify the input by opposite gains
• Here, V out

/ V

in = - g m

R

D and V out

/ V

in = +g m

R

D

• If I 1 and I 2 vary in opposite directions, so do | Vout1 / Vin | and | V out

/ V

in