8086 Architecture By Er. Swapnil V. Kaware, Lecture notes of Microprocessors

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8086 ARCHITECTURE

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Microprocessor Notes by Er. Swapnil V. Kaware (svkaware@yahoo.co.in)

8086 ARCHITECTURE Presented By, Er. Swapnil V. Kaware (Assistant Professor) svkaware@yahoo.co.in B.E.(Electronics), M.E.( Electronics)

8086 Architecture Microprocessor Notes By, Er. Swapnil

• 8086 internal Architecture contains mainly following two units.
• (1). BIU (Bus Interface Unit).
• (2). EU (Execution Unit).
• BIU contains Instruction queue, Segment registers,Instruction pointer,etc.
• EU contains Control circuitry, Instruction decoder, ALU,Pointer and Index register, Flag register,etc. 8086 Internal Architecture Microprocessor Notes By, Er. Swapnil

(8). The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. (9). If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. (10). The BIU also contains a dedicated adder which is used to generate the 20bit physical address. Microprocessor Notes By, Er. Swapnil Bus Interface Unit (BIU)

(1). The Execution unit is responsible for decoding and executing all instructions. (2). The EU extracts instructions from the top of the queue in the BIU. (3). During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. Execution Unit (EU) Microprocessor Notes By, Er. Swapnil

8086’s Fourteen 16-Bit Registers

ES

CS

SS

DS

IP

AH

BH

CH

DH

AL

BL

CL

DL

SP

BP

SI

DI

FLAGS

AX

BX

CX

DX

Extra Segment

Code Segment

Stack Segment

Data Segment

Instruction Pointer

Accumulator

Base Register

Count Register

Data Register

Stack Pointer

Base Pointer

Source Index Register

Destination Index Register

BIU registers

(20 bit adder)

EU registers

16 bit arithmetic

Microprocessor Notes By, Er. Swapnil

Instruction Queue

• It is of 6 Bytes.
• To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory.
• It operates on the principle first in first out (FIFO).
• Then all bytes are given to EU one by one.
• This pre-fetching operation of BIU may be in parallel with execution operation of EU.
• It improves the execution speed of the instruction. Microprocessor Notes By, Er. Swapnil

General Purpose Registers

• There are four 16-bit general purpose registers:
• AX
• BX
• CX
• DX Microprocessor Notes By, Er. Swapnil

• Each of these 16-bit registers are further subdivided into two 8-bit registers. General Purpose Registers AH AL BH BL CH CL DH DL AX BX CX DX Microprocessor Notes By, Er. Swapnil

Pointer & Index Register

• Following four registers are under this category:
• (1). Stack Pointer (SP),
• (2). Base Pointer (BP),
• (3). Source Index (SI),
• (4). Destination Index (DI). Microprocessor Notes By, Er. Swapnil

• Following Registers can also be used as a general Purpose Registers. (1). Stack Pointer (SP) is a 16-bit register pointing to program Stack, also contains 16-Bit offset address. (2). Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based indexed or register indirect addressing. (3). Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation Instructions (4). Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Pointer & Index Register Microprocessor Notes By, Er. Swapnil

• A segment register points to the starting address of a memory segment.
• For e.g.:
• The code segment register points to the starting address of the code segment.
• The data segment register points to the starting address of the data segment, and so on.
• The maximum capacity of a segment may be up to 64 KB. Segment Register Microprocessor Notes By, Er. Swapnil

• Code segment (CS):-
• It is a 16-bit register containing address of 64 KB segment with processor instructions.
• The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register.
• CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions Segment Register Microprocessor Notes By, Er. Swapnil