4-bit Register with Load Control
–Controlling the load capability
Q
3 Q
2 Q
1 Q
0
Clock
Parallel input
Parallel output
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Load
Docsity.com
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Guidelines and tips
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Community
Ask the community
Ask the community for help and clear up your study doubts
University Rankings
Discover the best universities in your country according to Docsity users
Free resources
Our save-the-student-ebooks!
Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors
4-Bit Register - Computer Organization and Design - Lecture Slides, Slides of Computer Aided Design (CAD)
The digital system design, is very helpful series of lecture slides, which made programming an easy task. The major points in these laboratory assignment are:4-Bit Register, Load Control, Parallel Input, Controlling Load Capability, Data Sizes, Register File, Bit Widths, Register File Implementation, Binary Value, Decoder, Data in Processor, Parallel Output
Typology: Slides
2012/2013
1 / 6
This page cannot be seen from the preview
Don't miss anything!
Related documents
Partial preview of the text
Download 4-Bit Register - Computer Organization and Design - Lecture Slides and more Slides Computer Aided Design (CAD) in PDF only on Docsity!
4-bit Register with Load Control
– Controlling the load capability
Q
Q
Q
Q
Clock
Parallel input
Parallel output
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Load
Data Sizes
• We’ve see 4-bits…
• Q: How many bits is “typical” data in a processor?
• A: It depends on the architecture
- 4-bit, 8-bit, 32-bit, etc. (usually powers of 2)
- This is often described as “word size”
• It is useful, architecturally, to keep a group of these
around for the programmer to use explicitly
- Y = A + B
- We’ll get back to this later…
Register File Implementation
3 x 8 decoder
register 0
register 1
register 2
register 3
register 4
register 5
register 6
register 7
8x MUX
8x MUX
RegWrite
D D D D D D D D W
W
W
W
W
W
W
W
(Same inputs
as mux above)
WriteReg
ReadReg
ReadReg
ReadData
ReadData
WriteData
What is a Decoder?
- Input is a binary value, output is “one-asserted”
- Exactly one output line is 1
- 2x4 decoder has 2 inputs and 4 outputs
0
1
2
3
Input Output
00 0001
01 0010
10 0100
11 1000