193971172 advanced computer architecture, Exams of Advanced Computer Architecture

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Biyani's Think Tank

Concept based notes

Advanced Computer Architecture

(BCA-III Year)

Nitika Newar, MCA Revised By: Namarta

Dept. of Information Technology

Biyani Girls College, Jaipur

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Preface

I am glad to present this book, especially designed to serve the needs of the students.

The book has been written keeping in mind the general weakness in understanding the fundamental concepts of the topics. The book is self-explanatory and adopts the “Teach Yourself” style. It is based on question-answer pattern. The language of book is quite easy and understandable based on scientific approach.

Any further improvement in the contents of the book by making corrections, omission and inclusion is keen to be achieved based on suggestions from the readers for which the author shall be obliged.

I acknowledge special thanks to Mr. Rajeev Biyani, Chairman & Dr. Sanjay Biyani, Director ( Acad. ) Biyani Group of Colleges, who are the backbones and main concept provider and also have been constant source of motivation throughout this Endeavour. They played an active role in coordinating the various stages of this Endeavour and spearheaded the publishing work.

I look forward to receiving valuable suggestions from professors of various educational institutions, other faculty members and students for improvement of the quality of the book. The reader may feel free to send in their comments and suggestions to the under mentioned address.

Author

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Syllabus

B.C.A. Part-III

Advanced Computer Architecture

Parallel Computer Models : The state of computing, multiprocessors and multicomputer, multivector and SIMD computers, architectural development tracks.

Program and Network Properties : Conditions of parallelism, program partitioning and scheduling, program flow mechanisms.

System Interconnect Architectures : Network properties and routing, Static interconnection network and dynamic intercommection networks.

Processors and Memory Hierachy : Advanced processor technology—CISC, RISC, Superscalar, Vector VLIW and symbolic processors, memory technology.

Bus, Cache and Shared Memory. Linear Pipeline Processors, Nonlinear Pipeline, processors Instruction pipeline Design Multiprocessors System Interconnects Vector Processing Principles, Multivector Multiprocessors.

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5. Pipeline processors 5.1 Characteristics of Pipeline 5.2 Linear pipeline processors 5.3 Non Linear pipeline processors 5.4 Reservation table in linear pipelining & non linear pipelining 5.5. Instruction pipeline design 5.6 Arithmetic pipeline design

6. Unsolved Papers 2011 - 2006

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Chapter 1

Parallel Computer Models

Q.1. What is multiprocessors? What are the types of multi-processors?

Ans. A multiprocessor structure is an interconnection of two or more than two CPUs with memory as input-output apparatus. Multiprocessors are grouped as multiple instruction stream, multiple data stream (MIMD) systems. some similarities are found between multiprocessor & multicomputer organization since both support simultaneous operations. However there is an important peculiarity between a system with multiple computers & a system with multiple processors. Computers are interconnected with each other with communication lines to make a computer network. The network comprise of numerous autonomous computers that may or may not converse with each other. A multiprocessor system is governed by one operating system that present inter-connection between processors & all the units of the system assist in the solution of a problem very large scale integrated circuit technology has abridged the cost of computer to such a low level that the concept of applying multiple processors to meet system performance needs has turn out to be an smart design prospect. Multiprocessing develop the trustworthiness of system so that a failure or error in one part has narrowed impact on rest of system. If a fault roots one processor to fail, a second processor can be allocated to complete the functions of disabled processor. The entire system can keep on functioning suitably with possibly some loss in efficiency. The benefits resulting from a multiprocessor organisation is better system performance. The system derives its high performance from the fact that manipulation can advance in parallel in one of two ways:

1. Multiple independent tasks can be completed to work in parallel.
2. A single task can be divided into multiple parallel tasks.

Example 1. a computer system where are processor performs the computations for an industrial process control while others monitors control various parameter such as temperature and flow rate.

Example 2. a computer where are processor performs high speed floating point mathematical computations and another take care of routine data processing tasks.

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concurrent data processing to attain faster execution time. The idea of parallel processing is to speed up the computer processing capability also increase its throughput, i.e., the amount of processing that can be done during an interval of time. Parallel processing at higher level of complexity can be realized by including multiplicity of functional units that do identical or different operations concurrently. Parallel processing is recognized by giving out the data among the multiple functional units. For example the arithmetic logic and shift operations

can be alienated into three units and the operands diverted to each unit under the supervision of control unit. Singe Instruction stream – Single Data Stream (SISD) IS

CU

IS PU

DS MM

Single Instruction Multiple Data Stream (SIMD)

PU 1 DS^1 MM 1

PU 2

DS 2 MM 2 CU

PUn

DSn MMn

IS CU: Control Unit PU: Processing Unit MM: Memory Module These are divers of ways that parallel processing can be classified. One classification introduced by M.J. Flynn considers the organization of computer

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system by number of instructions and data items that are manipulated simultaneously. The normal operation of a computer is to fetch instructions from memory and execute them in the processor. The sequence of instructions read from memory constitutes an instruction stream. The operations performed on the data is processor constitutes a data stream parallel processing may be occur in the instruction stream, in data stream or both. Single instruction stream, single Data stream (SISD) Single instruction stream, multiple data stream (SIMD) Multiple instruction stream, single data stream (MISD) Multiple instruction stream, multiple data stream (MIMD)

CU 1 IS^1 PU 1

CU 2 PU 2

CUn

ISn

MMn

IS 2

MM 1 MM 2

IS 1

IS 2

IS 3 PUn^ DS

ISn IS 2 IS 1

Multiple Instruction Stream Single Data Stream (MISD)

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(1955-64)

Third (1965-74)

Fourth (1975-90)

Fifth ( present)

Discrete transistors and core memories, floating point arithmetic, I/O processors, multiplexed memory access. Integrated circuits (SSI-MSI), microprogramming, pipelining, cache & lookahead processors. LSI/VLSI & semi conductor memory, multiprocessors, vector supercomputers, multi computers. ULSI/VHSIC processors, memory & switches, high density packaging, scalable architectures.

HLL used with compilere, subroutine libraries, batch processing monitor. Multiprogramming & time sharing OS, multi user applications. Multiprocessor OS, languages, compilers & environment for parallel processing. Massively parallel processing, grand challenge applications, heterogenous processing.

IBM 7090, CDC 1604, Univac LARC.

IBM 360/370, CDC 6600, TI- ASC, PDP- 8 VAX 9000, Gay XMP, IBM 3090 BBN TC 2000 Fujitsu VPP 500, Gay/MPP, TMC/CM-5, Intel paragon.

In other words, the latest generation computers have inherited all the bad ones found in previous generations.

Q.4. How is computer Architecture developed?

Ans. Over the past four decades, computer architecture has gone through evolutional rather than revolution changes sustaining features are those that were proven performance delivers. According to the figure we started with the Von Neumann architecture built as a sequential machine executing scalar data. Sequential computers improved from bit serial to word-parallel operations & from fixed point to floating point operations. The Von Neumann architecture is slow due to sequential execution of instructions in programme.

Lookahead, Paralleism and Pipelining : Lookahead techniques were begin to prefetch instructions in order to overlap I/E (instruction fetch/decode and execution) operations and to enable functional parallelism. Functional parallelism was supported by two approaches: One is to use multiple functional units simultaneously and the other is to practice pipelining at various processing levels. The latter embrace pipelined instruction execution, pipelined arithmetic computations and memory access operations. Pipelining has proven especially attractive in performing identical operations repeatedly over vector data strings. Vectors operations were originally carried out implicitly by software controlled looping using scalar pipeline processors. Flynn’s Classification: Michael Flynn (1972) established nomenclature of a variety of computer architectures based on concept of instruction and data

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streams. Traditional sequential machines are SISD (single instruction stream over a single data stream). Vector computers are set with scalar and vector hardware or emerge as SIMD (single instruction stream over multiple data streams). Parallel computers are called MIMD (multiple instruction streams over multiple data streams) machines.

Q.5. What is Parallelism? What are the various conditions of parallelism

Ans. Parallelism is the major concept used in today computer use of multiple functional units is a form of parallelism within the CPU. In early computer only one arithmetic & functional units are there so it cause only one operation to execute at a time. So ALU function can be distributed to multiple functional units, which are operating in parallel. H.T. Kung has recognized that there is a need to move in three areas namely computation model for parallel computing, inter process communication in parallel architecture & system integration for incorporating parallel systems into general computing environment. Conditions of Parallelism :

1. Data and resource dependencies : A program is made up of several part, so the ability of executing several program segment in parallel requires that each segment should be independent other segment. Dependencies in various segment of a program may be in various form like resource dependency, control depending & data depending. Dependence graph is used to describe the relation. Program statements are represented by nodes and the directed edge with different labels shows the ordered relation among the statements. After analyzing dependence graph, it can be shown that where opportunity exist for parallelization & vectorization. Data Dependencies: Relation between statements is shown by data dependences. There are 5 types of data dependencies given below: (a) Antidependency: A statement S 2 is antidependent on statement ST 1 if ST 2 follows ST 1 in order and if the output of ST 2 overlap the input to ST 1. (b) Input dependence: Read & write are input statement input dependence occur not because of same variables involved put because of same file is referenced by both input statements. (c) Unknown dependence: The dependence relation between two statement cannot be found in following situation The subscript of variable is itself subscribed. The subscript does not have the loop index variable. Subscript is non linear in the loop index variable.

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parallelism is greater than two but the average parallelism at instruction level is around fine rarely exceeding seven in ordinary program. For scientific applications average parallel is in the range of 500 to 300 fortran statements executing concurrently in an idealized environment.

2. Loop Level : It embrace iterative loop operations. A loop may contain less than 500 instructions. Some loop independent operation can be vectorized for pipelined execution or for look step execution of SIMD machines. Loop level parallelism is the most optimized program construct to execute on a parallel or vector computer. But recursive loops are different to parallelize. Vector processing is mostly exploited at the loop level by vectorizing compiler. 3. Procedural Level : It communicate to medium grain size at the task, procedure, subroutine levels. Grain at this level has less than 2000 instructions. Detection of parallelism at this level is much more difficult than a finer grain level. Communication obligation is much less as compared with that MIMD execution mode. But here major efforts are requisite by the programmer to reorganize a program at this level. 4. Subprogram Level : Subprogram level communicate to job steps and related subprograms. Grain size here have less than 1000 instructions. Job steps can overlap across diverse jobs. Multiprogramming an uniprocessor or multiprocessor is conducted at this level. 5. Job Level : It corresponds to parallel executions of independent tasks on parallel computer. Grain size here can be tens of thousands of instructions. It is handled by program loader and by operating system. Time sharing & space sharing multiprocessors explores this level of parallelism.

Q.7. Explain Vector super computers?

Ans. Program & data are first loaded into the main memory from a host computer. All instructions are first decoded by the scalar control unit. If the decoded instruction is a scalar operation or program control operation it will be directly executed by scalar processor using the scalar functional pipelines. If the instruction is decoded as a vector procedure, it will be sent to the vector control unit. This control unit will supervise the flow of vector data amid the main memory & vector functional pipelines. The vector data flow is synchronized by control unit. A number of vector functional pipelines may be built into a vector processor.

Computers with vector processing capabilities are in demand in specialized applications. The following are symbolized application areas where vector processing is of utmost importance. Long Range weather forecasting

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Petroleum explorations Medical diagnosis Space flight simulations Vector Processor Models Scalar Processor Scalar Functional Pipelines Scalar Instructions Scalar control unit Instructions Main menory

Scalar data

Mass storage

Host computer

Vector registers

Vector func. pipe

Vector function pipe

Control

Vector control unit

Vector processor

The Architecture of vector super computer

Q.8. What are the different shared memory multiprocessor models?

Ans. The most popular parallel computers are those that execute programs in MIMD mode. There are two major classes of parallel computers: shared memory multiprocessor & message – passing multi computers. The major distinction between multiprocessors & multicomputers lies in memory sharing and the mechanisms used for interprocessor communication. The processor in multiprocessor system communicate with each other through shared variable in a common memory. Each computer node in a multicomputer system has a local memory, unshared with other nodes. Inter process communication is done through message passing among nodes.

There are three shared memory multiprocessor models:-

1. Uniform memory access (UMA) model
2. Non-uniform memory access (NUMA) model
3. Cache only memory Architecture (COMA) model These models are differ in how the memory & peripheral resources are shared or distributed. 1. UMA Model:

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LM 1

LM 2

LMn

P 1

P 2

Pn

Inter Connection Network

Shared Local Memories In the hierarchial cluster Model processors are divided into several clusters. Each cluster may be UMA or NUMA Each cluster is connected to shared memory modules. All processors of a single cluster uniformally access the cluster shared memory modules. All cluster equally access to global memory access time to cluster memory is shorter then that of global memory.

GSM GSM^ GSM

Global Interconnect Network

P 1

P 2

Pn

CSM

CSM

CSM

P 1

P 2

Pn

CSM

CSM

CSM

C

I

N

C

I

N

A hierarchical cluster models

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3. Cache Only Memory Architecture: This model is a special case of NUMA machine where distributed main memories are replaced with cache memory. At individual processor node, there is no memory chain of command(hierarchy). All cache made a global address space. Depending on interconnection network used, directories may be used to help in locating copies of cache blocks example of COMA includes Swedish Institute of Computer Science‘s Data Diffusion machine (DDM). Interconnection Network

D

C

P

D

C

P

D

C

P

Q.9. What is Distributed Memory Multicomputers?

Ans. A system made up of multiple computers( nodes), interconnected by a message passing network. Each node is autonomous computer consisting of a processor, local memory and from time to time attached disks or I/O peripherals.

M P

M P

M P

M P

M P

M P

M P

M P

M P

M P

Message passing inter- connection network (mesh, ring etc.)